The present invention relates to a signal processing system for a magnetic disk device, an optical disk device or the like, and more particularly to a signal processing method and apparatus suitable for the reduction in power consumption of a circuit or LSI.
Recently, a partial response maximum likelihood (hereinafter abbreviated to PRML) decoding system is put into practice as a high-efficiency signal processing system in a magnetic disk device. The high-efficiency signal processing system means a system which can realize a desired data error rate at a low S/N.
FIG. 17 shows an example of the construction of a general magnetic disk device using a PRML signal processing system. The original data is supplied to an encoder 7 for error correction code (ECC) through an interface circuit 8 so that it is added with redundant data necessary for error correction. Next, the original data added with redundant data is subjected by a data modulator 6 to modulation necessary for the PRML system and is recorded on a magnetic disk 3 by a magnetic head 4 through a recording/reproducing amplifier 5. A signal reproduced from the magnetic disk is passed through the recording/reproducing amplifier 5 and then PRML-processed by a data demodulator 71. The demodulated data is error-corrected by a decoder 2 for error correction code and is thereafter converted through the interface circuit 8 into the original data. With such a recording/reproducing process, the reproduction of a low S/N signal is performed. An extended PRML (EPRML) system, an extended EPRML (EEPRML) system, a TRELLIS demodulation system and so forth are investigated as signal processing systems which make the reproduction of a lower-S/N signal possible.
On the other hand, the concept of data demodulation with connection code positioned as a super-ordinate concept of the signal processing system has been proposed. A known example includes "Producing Soft-Decision Information at the Output of a Class-IV Partial Response Viterbi Detector", International Conference on Communications '91 Conference Record, Volume 2 of 3. This known system is constructed to perform the demodulation of data by combining two signal processing systems as shown in FIG. 18. First, the data demodulator 71 is used at an initial stage to perform the demodulation of data and the extraction of information which gives the reliability of that data. The result of data demodulation at the initial stage is supplied to the next stage formed by the decoder 2 for error correction code which performs the decoding of data at a high efficiency by utilizing the data reliability information. Thus, a connection code scheme utilizing the data reliability information with the coupling thereof with the error correction code decoding system being hitherto taken into consideration is investigated as an effective system for realizing the high-efficiency signal processing system.
In the signal processing system suitable for the implementation of high efficiency and the data demodulating system using the connection code, as mentioned above, high-efficiency data demodulation is attained but an operation processing for performing data demodulation is exponentially complicated. In general, a signal processing circuit having a low data discriminating capability (for example, the PRML system) is simple in data discriminating method and small in both circuit scale and power consumption whereas a signal processing circuit having a high data discriminating capability (for example, the EPRML system or the TRELLIS system) is complicated in circuit and large in power consumption. Accordingly, a signal processing LSI for performing the data demodulation of a low-S/N signal has an increase in scale of an operating circuit and an increase in power consumption thereof. The increase in power consumption results in a substantial hindrance to the realization of a signal processing LSI.